library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;
    
entity WE_Logic is
    port(R_W, Data_Size: in  bit;
         MAR_out: in unsigned(15 downto 0);
         WE0, WE1: out bit);
end entity WE_Logic;

architecture build of WE_Logic is
    begin
        process(R_W,MAR_out,Data_Size)
            begin
                if   R_W = '1' then
                   if      Data_Size = '1' then
                      WE0 <= '1';
                      WE1 <= '1';
                   elsif   MAR_out(0) = '1' then
                      WE0 <= '0';
                      WE1 <= '1';
                   elsif   MAR_out(0) = '0' then
                      WE0 <= '1';
                      WE1 <= '0';
                   end if;
               end if;
            end process;
    end build;